The present invention relates to a data processor and, more particularly, to a processor performing an operation on data having a short data length.
A data processor is often required to process data which includes a smaller number of bits than the usual processing words. For example, in a 32-bit processor in which one word consists of 32 bits, it is also required to process data of 16-bit length (i.e., half-word length) or 8-bit length (i.e., quarter-word or one-byte length) in addition to processing data of usual 32-bit word. The information for designating the length of data to be processed is contained in an instruction to be executed. It should be noted, however, that in order to simplify a hardware, the data processor executes an operation in word unit and performs data read/write operation in a word unit. That is, it is impossible to execute an operation only on the data of the designated length and to perform an write operation only of the resultant data into a destination register. On the other hand, the instruction designating an operation on the data of half-word or quarter-word length requests that the operation result is written into the corresponding portion of the destination register with the remaining portion thereof holding previous data.
For this purpose, a data processor according to the prior art includes a blocking register on the output side of an operation unit. When it is designated to process data of half-word or quarter-word length, the blocking register is controlled to temporarily store in its one portion the operation result corresponding to the designated data length and in the remaining portion the data of the corresponding portion of the destination register. In the case of designating an operation which processes data of one-word length, the blocking register is controlled to store data of full bits of the operation result. The data stored in the blocking register is thereafter transferred onto a data bus and written into the destination register. As a result, the instruction designating an operation on the data of half-word or quarter-word length as well as one-word length is executed.
However, the blocking register is provided on the output side of the operation unit to store full or partial bits of the operation result data. For this reason, if a plurality of operation units such as an arithmetic and logic unit, a multiplier, a shifter and the like are required, the number of the blocking registers is increased accordingly. Moreover, the operation result data is temporarily stored in the blocking register and thereafter transferred onto the data bus, so that an operation speed is lowered.